1. Field of the Invention
The invention relates to a circuit configuration having a number of electronic circuit components. The operating state of the circuit components can be set to a reset or erase state by a predetermined control signal which is applied to the respective circuit component, in which state the data content of the circuit component assumes a logic zero value.
For various reasons, it may be necessary to erase individual registers or the complete content of a semiconductor memory integrated on a microprocessor chip or of a further circuit component. Particularly in smart card applications, it may be desirable, as protection against the unauthorized read-out of confidential data, to provide actively operating protective measures for preventing a read-out of secret data in the event of a hacker attack, for example, even when the clock supply of the microprocessor is disconnected. When the microprocessor is switched on, all of the registers are, as a rule, preassigned a defined value that is exchanged for different data contents in the course of data processing, which data contents may, under certain circumstances, also include confidential or personal values. In order to preassign a predetermined, defined value to the registers, the latter are usually provided with a separately provided reset input. The reset input passes, for example, to a switching transistor that brings the register value to a defined potential. In the case of a random access semiconductor memory having a multiplicity of memory cells, the provision of separate reset inputs for each memory cell would greatly increase the area requirement. In addition, this procedure requires a large driver power for resetting the memory since, for example, 256.times.8 transistors must be driven simultaneously. Such a configuration would contradict not only the desire for a maximum integration level of a semiconductor memory but also a construction of the selection circuits which saves current and is as simple as possible. An active protective measure against unauthorized access to confidential data that might furthermore be conceived of is, by use of the microprocessor, to address successively all the relevant memory cells of the semiconductor device and subsequently to overwrite every addressed memory cell with the logic zero value. However, such a solution is not successful in preventing unauthorized data access in all cases, since it is possible to inhibit the clock supply, the microprocessor stops and cannot perform any tasks.
From U.S. Pat. No. 4,928,266, there is known a selection circuit with a chain of n-delay elements, whose first RESET is selected by an internal reset signal, and a multiplicity of n-reset-drivers, each of which is selected by a delay element. The purpose of the phase-shifted selection is to reduce the current peaks caused by the reset signals.
A chain of "flash-clear" circuits which are addressed chronologically delayed successively, whereby the circuit is activated by a start signal by a starting circuit is disclosed in European Patent Application EP 0 574 094 A, corresponding to U.S. Pat. Nos. 5,054,000 and 5,047,985. The reference further shows, with respect to the circuit, a simplified version of the "flash-clear" circuit with a ring oscillator. The ring oscillator has an oscillating holding function for generating clock pulses which are used for setting the erase time with a counter for counting the number of output clock pulses of the ring oscillator, and a m-bit counter for counting the number of memory cell groups.
International Patent Application WO 82 022 74 A discloses a configuration for the automatic erasing of the data contents in data banks of a particular circuit. An "emergency circuit", which after actuation in a first step controls the erasing of all data information in the data bank and then, in a second step, the erasing of all program information in the data bank. This particular circuit configuration serves primarily for erasing a data bank before unauthorized access or sabotage occurs without physically destroying it. The circuit configuration has a bistable flip-flop operable by an emergency button, whose output signal activates the address generators controlled by the system clock, that is to say, all addresses are generated, which can occur in the connected data memories. The address generators operate in parallel to one another.
A configuration for protecting data against unauthorized access in a control unit of a coin-operated automated machine is disclosed in Published, Non-prosecuted German Patent Application DE 41 35 767 A. Sensors detect any attempt at opening the housing that protects the control unit. The sensors which detect a mechanical or chemical access, a change in ambient temperature, as well as an operating voltage, are connected to a sensor technique with its own power supply. The data in the data-relevant components are erased by an erasing circuit when accessing the control unit.